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Memristor crossbars are circuits capable of performing analog matrix-vectormultiplications, overcoming the fundamental energy efficiency limitations ofdigital logic. They have been shown to be effective in special-purposeaccelerators for a limited set of neural network applications.  We present the Programmable Ultra-efficient Memristor-based Accelerator(PUMA) which enhances memristor crossbars with general purpose execution unitsto enable the acceleration of a wide variety of Machine Learning (ML) inferenceworkloads. PUMA's microarchitecture techniques exposed through a specializedInstruction Set Architecture (ISA) retain the efficiency of in-memory computingand analog circuitry, without compromising programmability.  We also present the PUMA compiler which translates high-level code to PUMAISA. The compiler partitions the computational graph and optimizes instructionscheduling and register allocation to generate code for large and complexworkloads to run on thousands of spatial cores.  We have developed a detailed architecture simulator that incorporates thefunctionality, timing, and power models of PUMA's components to evaluateperformance and energy consumption. A PUMA accelerator running at 1 GHz canreach area and power efficiency of $577~GOPS/s/mm^2$ and $837~GOPS/s/W$,respectively. Our evaluation of diverse ML applications from image recognition,machine translation, and language modelling (5M-800M synapses) shows that PUMAachieves up to $2,446\times$ energy and $66\times$ latency improvement forinference compared to state-of-the-art GPUs. Compared to anapplication-specific memristor-based accelerator, PUMA incurs small energyoverheads at similar inference latency and added programmability.

PUMA: A Programmable Ultra-efficient Memristor-based Accelerator for Machine Learning Inference