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Analog-to-digital converters (ADCs) are a major contributor to the powerconsumption of multiple-input multiple-output (MIMO) communication systems withlarge number of antennas. Use of low resolution ADCs has been proposed as ameans to decrease power consumption in MIMO receivers. However, reducing theADC resolution leads to performance loss in terms of achievable transmissionrates. In order to mitigate the rate-loss, the receiver can perform analogprocessing of the received signals before quantization. Prior works considerone-shot analog processing where at each channel-use, analog linearcombinations of the received signals are fed to a set of one-bit thresholdADCs. In this paper, a receiver architecture is proposed which uses a sequenceof delay elements to allow for blockwise linear combining of the receivedanalog signals. In the high signal to noise ratio regime, it is shown that theproposed architecture achieves the maximum achievable transmission rate given afixed number of one-bit ADCs. Furthermore, a tradeoff between transmission rateand the number of delay elements is identified which quantifies the increase inmaximum achievable rate as the number of delay elements is increased.

Tradeoff Between Delay and High SNR Capacity in Quantized MIMO Systems