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Power side-channel attacks (SCAs) have become a major concern to the securitycommunity due to their non-invasive feature, low-cost, and effectiveness inextracting secret information from hardware implementation of cryto algorithms.Therefore, it is imperative to evaluate if the hardware is vulnerable to SCAsduring its design and validation stages. Currently, however, there islittle-known effort in evaluating the vulnerability of a hardware to SCAs atearly design stage. In this paper, we propose, for the first time, an automatedframework, named RTL-PSC, for power side-channel leakage assessment of hardwarecrypto designs at register-transfer level (RTL) with built-in evaluationmetrics. RTL-PSC first estimates power profile of a hardware design usingfunctional simulation at RTL. Then it utilizes the evaluation metrics,comprising of KL divergence metric and the success rate (SR) metric based onmaximum likelihood estimation to perform power side-channel leakage (PSC)vulnerability assessment at RTL. We analyze Galois-Field (GF) and Look-up Table(LUT) based AES designs using RTL-PSC and validate its effectiveness andaccuracy through both gate-level simulation and FPGA results. RTL-PSC is alsocapable of identifying blocks inside the design that contribute the most to thePSC vulnerability which can be used for efficient countermeasureimplementation.

RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level