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The evolution of IoT based smart applications demand porting of artificialintelligence algorithms to the edge computing devices. CNNs form a large partof these AI algorithms. Systolic array based CNN acceleration is being widelyadvocated due its ability to allow scalable architectures. However, CNNs areinherently memory and compute intensive algorithms, and hence pose significantchallenges to be implemented on the resource-constrained edge computingdevices. Memory-constrained low-cost FPGA based devices form a substantialfraction of these edge computing devices. Thus, when porting to suchedge-computing devices, the designer is left unguided as to how to select asuitable systolic array configuration that could fit in the available hardwareresources. In this paper we propose Systimator, a design space explorationbased methodology that provides a set of design points that can be mappedwithin the memory bounds of the target FPGA device. The methodology is basedupon an analytical model that is formulated to estimate the required resourcesfor systolic arrays, assuming multiple data reuse patterns. The methodologyfurther provides the performance estimates for each of the candidate designpoints. We show that Systimator provides an in-depth analysis ofresource-requirement of systolic array based CNNs. We provide our resourceestimation results for porting of convolutional layers of TINY YOLO, a CNNbased object detector, on a Xilinx ARTIX 7 FPGA.

Systimator: A Design Space Exploration Methodology for Systolic Array based CNNs Acceleration on the FPGA-based Edge Nodes