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Ubiquitous multicore processors nowadays rely on an integratedpacket-switched network for cores to exchange and share data. The performanceof these intra-chip networks is a key determinant of the processor speed and,at high core counts, becomes an important bottleneck due to scalability issues.To address this, several works propose the use of mm-wave wirelessinterconnects for intra-chip communication and demonstrate that, thanks totheir low-latency broadcast and system-level flexibility, this new paradigmcould break the scalability barriers of current multicore architectures.However, these same works assume 10+ Gb/s speeds and efficiencies close to 1pJ/bit without a proper understanding on the wireless intra-chip channel. Thispaper first demonstrates that such assumptions do not hold in the context ofcommercial chips by evaluating losses and dispersion in them. Then, we leveragethe system's monolithic nature to engineer the channel, this is, to optimizeits frequency response by carefully choosing the chip package dimensions.Finally, we exploit the static nature of the channel to adapt to it, pushingefficiency-speed limits with simple tweaks at the physical layer. Our methodsreduce the path loss and delay spread of a simulated commercial chip by 47 dBand 7.3x, respectively, enabling intra-chip wireless communications over 10Gb/s and only 3.1 dB away from the dispersion-free case.

Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication