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With the High Luminosity LHC upgrades, incorporating tracking informationinto the CMS Level-1 trigger becomes necessary in order to maintain amanageable trigger rate and good trigger performance e.g. to retain thresholdsfor electroweak physics. The main challenges Level-1 track finding faces arethe large data throughput from the detector at a collision rate of 40 MHz and a4 microsecond latency budget to reconstruct charged particle tracks withsufficiently low transverse momentum to be used in the Level-1 triggerdecision. Dedicated all-FPGA hardware systems with time-multiplexedarchitecture have been developed for track finding to address these challenges.The algorithm and performance of the pattern recognition and particletrajectory determination are discussed. The implementation on customizedelectronics with commercially available FPGAs is presented as well.

Level-1 Track Finding with an all-FPGA system at CMS for the HL-LHC