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Recurrent Neural Networks (RNNs) are becoming increasingly important for timeseries-related applications which require efficient and real-timeimplementations. The two major types are Long Short-Term Memory (LSTM) andGated Recurrent Unit (GRU) networks. It is a challenging task to havereal-time, efficient, and accurate hardware RNN implementations because of thehigh sensitivity to imprecision accumulation and the requirement of specialactivation function implementations.  A key limitation of the prior works is the lack of a systematic designoptimization framework of RNN model and hardware implementations, especiallywhen the block size (or compression ratio) should be jointly optimized with RNNtype, layer size, etc. In this paper, we adopt the block-circulant matrix-basedframework, and present the Efficient RNN (E-RNN) framework for FPGAimplementations of the Automatic Speech Recognition (ASR) application. Theoverall goal is to improve performance/energy efficiency under accuracyrequirement. We use the alternating direction method of multipliers (ADMM)technique for more accurate block-circulant training, and present two designexplorations providing guidance on block size and reducing RNN training trials.Based on the two observations, we decompose E-RNN in two phases: Phase I ondetermining RNN model to reduce computation and storage subject to accuracyrequirement, and Phase II on hardware implementations given RNN model,including processing element design/optimization, quantization, activationimplementation, etc. Experimental results on actual FPGA deployments show thatE-RNN achieves a maximum energy efficiency improvement of 37.4$\times$ comparedwith ESE, and more than 2$\times$ compared with C-LSTM, under the sameaccuracy.

E-RNN: Design Optimization for Efficient Recurrent Neural Networks in FPGAs