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Domain specific accelerators present new challenges and opportunities forcode generation onto novel instruction sets, communication fabrics, and memoryarchitectures.  In this paper we introduce an intermediate representation (IR) which enablesboth deep learning computational kernels and hardware capabilities to bedescribed in the same IR. We then formulate and apply instruction mapping todetermine the possible ways a computation can be performed on a hardwaresystem. Next, our scheduler chooses a specific mapping and determines the datamovement and computation order. In order to manage the large search space ofmappings and schedules, we developed a flexible framework that allowsheuristics, cost models, and potentially machine learning to facilitate thissearch problem.  With this system, we demonstrate the automated extraction of matrixmultiplication kernels out of recent deep learning kernels such asdepthwise-separable convolution. In addition, we demonstrate two to five timesbetter performance on DeepBench sized GEMMs and GRU RNN execution when comparedto state-of-the-art (SOTA) implementations on new hardware and up to 85% of theperformance for SOTA implementations on existing hardware.

ISA Mapper: A Compute and Hardware Agnostic Deep Learning Compiler