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Binarized Neural Network (BNN) removes bitwidth redundancy in classical CNNby using a single bit (-1/+1) for network parameters and intermediaterepresentations, which has greatly reduced the off-chip data transfer andstorage overhead. However, a large amount of computation redundancy stillexists in BNN inference. By analyzing local properties of images and thelearned BNN kernel weights, we observe an average of $\sim$78% input similarityand $\sim$59% weight similarity among weight kernels, measured by our proposedmetric in common network architectures. Thus there does exist redundancy thatcan be exploited to further reduce the amount of on-chip computations.  Motivated by the observation, in this paper, we proposed two types of fastand energy-efficient architectures for BNN inference. We also provide analysisand insights to pick the better strategy of these two for different datasetsand network models. By reusing the results from previous computation, muchcycles for data buffer access and computations can be skipped. By experiments,we demonstrate that 80% of the computation and 40% of the buffer access can beskipped by exploiting BNN similarity. Thus, our design can achieve 17%reduction in total power consumption, 54% reduction in on-chip powerconsumption and 2.4$\times$ maximum speedup, compared to the baseline withoutapplying our reuse technique. Our design also shows 1.9$\times$ morearea-efficiency compared to state-of-the-art BNN inference design. We believeour deployment of BNN on FPGA leads to a promising future of running deeplearning models on mobile devices.

Towards Fast and Energy-Efficient Binarized Neural Network Inference on FPGA