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Emerging non-volatile main memory (NVRAM) technologies providebyte-addressability, low idle power, and improved memory-density, and arelikely to be a key component in the future memory hierarchy. However, acritical challenge in achieving high performance is in accounting for theasymmetry that NVRAM writes can be significantly more expensive than NVRAMreads.  In this paper, we consider a large class of cache-oblivious algorithms fordynamic programming (DP) and linear algebra, and try to reduce the writes inthe asymmetric setting while maintaining high parallelism. To achieve that, ourkey approach is to show the correspondence between these problems and anabstraction for their computation, which is referred to as the $k$-d grids.Then by showing lower bound and new algorithms for computing $k$-d grids, weshow a list of improved cache-oblivious algorithms of many DP recurrences andin linear algebra in the asymmetric setting, both sequentially and in parallel.  Surprisingly, even without considering the read-write asymmetry (i.e.,setting the write cost to be the same as the read cost in the algorithms), thenew algorithms improve the existing cache complexity of many problems. Webelieve the reason is that the extra level of abstraction of $k$-d grids helpsus to better understand the complexity and difficulties of these problems. Webelieve that the novelty of our framework is of interests and leads to many newquestions for future work.

Improved Parallel Cache-Oblivious Algorithms for Dynamic Programming and Linear Algebra