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We propose a new DRAM-based true random number generator (TRNG) thatleverages DRAM cells as an entropy source. The key idea is to intentionallyviolate the DRAM access timing parameters and use the resulting errors as thesource of randomness. Our technique specifically decreases the DRAM rowactivation latency (timing parameter tRCD) below manufacturer-recommendedspecifications, to induce read errors, or activation failures, that exhibittrue random behavior. We then aggregate the resulting data from multiple cellsto obtain a TRNG capable of providing a high throughput of random numbers atlow latency.  To demonstrate that our TRNG design is viable using commodity DRAM chips, werigorously characterize the behavior of activation failures in 282state-of-the-art LPDDR4 devices from three major DRAM manufacturers. We verifyour observations using four additional DDR3 DRAM devices from the samemanufacturers. Our results show that many cells in each device produce randomdata that remains robust over both time and temperature variation. We use ourobservations to develop D-RanGe, a methodology for extracting true randomnumbers from commodity DRAM devices with high throughput and low latency bydeliberately violating the read access timing parameters. We evaluate thequality of our TRNG using the commonly-used NIST statistical test suite forrandomness and find that D-RaNGe: 1) successfully passes each test, and 2)generates true random numbers with over two orders of magnitude higherthroughput than the previous highest-throughput DRAM-based TRNG.

D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput