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In a superscalar processor, instructions of various types flow through anexecution pipeline, traversing hardware resources which are mostly shared amongmany different instruction types. A notable exception to shared pipelineresources is the collection of functional units, the hardware that performsspecific computations. In a trade-off of cost versus performance, a pipelinedesigner must decide how many of each type of functional unit to place in aprocessor's pipeline. In this paper, we model a superscalar processor's issuequeue and functional units as a novel queuing network. We treat the issue queueas a finite-sized waiting area and the functional units as servers. In additionto common queuing problems, customers of the network share the queue but waitfor specific servers to become ready (e.g., addition instructions wait foradders). Furthermore, the customers in this queue are not necessary ready forservice, since instructions may be waiting for operands. In this paper we modela novel queuing network that provides a solution to the expected queue lengthof each type of instruction. This network and its solution can also begeneralized to other problems, notably other resource-allocation issues thatarise in superscalar pipelines.

A Queuing Model for CPU Functional Unit and Issue Queue Configuration