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This paper investigates hardware-based memory compression designs to increasethe memory bandwidth. When lines are compressible, the hardware can storemultiple lines in a single memory location, and retrieve all these lines in asingle access, thereby increasing the effective memory bandwidth. However,relocating and packing multiple lines together depending on the compressibilitycauses a line to have multiple possible locations. Therefore, memorycompression designs typically require metadata to specify the compressibilityof the line. Unfortunately, even in the presence of dedicated metadata caches,maintaining and accessing this metadata incurs significant bandwidth overheadsand can degrade performance by as much as 40%. Ideally, we want to implementmemory compression while eliminating the bandwidth overheads of metadataaccesses.  This paper proposes CRAM, a bandwidth-efficient design for memory compressionthat is entirely hardware based and does not require any OS support or changesto the memory modules or interfaces. CRAM uses a novel implicit-metadatamechanism, whereby the compressibility of the line can be determined byscanning the line for a special marker word, eliminating the overheads ofmetadata access. CRAM is equipped with a low-cost Line Location Predictor (LLP)that can determine the location of the line with 98% accuracy. Furthermore, wealso develop a scheme that can dynamically enable or disable compression basedon the bandwidth cost of storing compressed lines and the bandwidth benefits ofobtaining compressed lines, ensuring no degradation for workloads that do notbenefit from compression. Our evaluations, over a diverse set of 27 workloads,show that CRAM provides a speedup of up to 73% (average 6%) without causingslowdown for any of the workloads, and consuming a storage overhead of lessthan 300 bytes at the memory controller.

CRAM: Efficient Hardware-Based Memory Compression for Bandwidth Enhancement