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Layout hotpot detection is one of the main steps in modern VLSI design. Atypical hotspot detection flow is extremely time consuming due to thecomputationally expensive mask optimization and lithographic simulation. Recentresearches try to facilitate the procedure with a reduced flow includingfeature extraction, training set generation and hotspot detection, wherefeature extraction methods and hotspot detection engines are deeply studied.However, the performance of hotspot detectors relies highly on the quality ofreference layout libraries which are costly to obtain and usually predeterminedor randomly sampled in previous works. In this paper, we propose an activelearning-based layout pattern sampling and hotspot detection flow, whichsimultaneously optimizes the machine learning model and the training set thataims to achieve similar or better hotspot detection performance with muchsmaller number of training instances. Experimental results show that ourproposed method can significantly reduce lithography simulation overhead whileattaining satisfactory detection accuracy on designs under both DUV and EUVlithography technologies.

Bridging the Gap Between Layout Pattern Sampling and Hotspot Detection via Batch Active Learning