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The C language is getting more and more popular as a design and verificationlanguage (DVL). SystemC, ParC [1] and Cx [2] are based on C. C-models of thedesign and verification environment can also be generated from new DVLs (e.g.Chisel [3]) or classical DVLs such as VHDL or Verilog. The execution of thesemodels is usually license free and presumably faster than their alternativecounterparts (simulators). This paper proposes activity-dependent, ordered,cycle-accurate (AOC) C-models to speed up simulation time. It compares theresults with alternative concepts. The paper also examines the execution of theAOC C-model on a multithreaded processor environment.

Deriving AOC C-Models from D&V Languages for Single- or Multi-Threaded Execution Using C or C++