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Convolutional Neural Networks have dramatically improved in recent years,surpassing human accuracy on certain problems and performance exceeding that oftraditional computer vision algorithms. While the compute pattern in itself isrelatively simple, significant compute and memory challenges remain as CNNs maycontain millions of floating-point parameters and require billions offloating-point operations to process a single image. These computationalrequirements, combined with storage footprints that exceed typical cache sizes,pose a significant performance and power challenge for modern computearchitectures. One of the promising opportunities to scale performance andpower efficiency is leveraging reduced precision representations for allactivations and weights as this allows to scale compute capabilities, reduceweight and feature map buffering requirements as well as energy consumption.While a small reduction in accuracy is encountered, these Quantized NeuralNetworks have been shown to achieve state-of-the-art accuracy on standardbenchmark datasets, such as MNIST, CIFAR-10, SVHN and even ImageNet, and thusprovide highly attractive design trade-offs. Current research has focusedmainly on the implementation of extreme variants with full binarization ofweights and or activations, as well typically smaller input images. Within thispaper, we investigate the scalability of dataflow architectures with respect tosupporting various precisions for both weights and activations, larger imagedimensions, and increasing numbers of feature map channels. Key contributionsare a formalized approach to understanding the scalability of the existinghardware architecture with cost models and a performance prediction as afunction of the target device size. We provide validating experimental resultsfor an ImageNet classification on a server-class platform, namely the AWS F1node.

Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic