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Deep neural networks (DNN) are increasingly being accelerated onapplication-specific hardware such as the Google TPU designed especially fordeep learning. Timing speculation is a promising approach to further increasethe energy efficiency of DNN accelerators. Architectural exploration for timingspeculation requires detailed gate-level timing simulations that can betime-consuming for large DNNs that execute millions of multiply-and-accumulate(MAC) operations. In this paper we propose FATE, a new methodology for fast andaccurate timing simulations of DNN accelerators like the Google TPU. FATEproposes two novel ideas: (i) DelayNet, a DNN based timing model for MAC units;and (ii) a statistical sampling methodology that reduces the number of MACoperations for which timing simulations are performed. We show that FATEresults in between 8 times-58 times speed-up in timing simulations, whileintroducing less than 2% error in classification accuracy estimates. Wedemonstrate the use of FATE by comparing to conventional DNN accelerator thatuses 2's complement (2C) arithmetic with an alternative implementation thatuses signed magnitude representations (SMR). We show that that the SMRimplementation provides 18% more energy savings for the same classificationaccuracy than 2C, a result that might be of independent interest.

FATE: Fast and Accurate Timing Error Prediction Framework for Low Power DNN Accelerator Design