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Deep neural networks are a biologically-inspired class of algorithms thathave recently demonstrated state-of-the-art accuracies involving large-scaleclassification and recognition tasks. Indeed, a major landmark that enablesefficient hardware accelerators for deep networks is the recent advances fromthe machine learning community that have demonstrated aggressively scaled deepbinary networks with state-of-the-art accuracies. In this paper, we demonstratehow deep binary networks can be accelerated in modified von-Neumann machines byenabling binary convolutions within the SRAM array. In general, binaryconvolutions consist of bit-wise XNOR followed by a population-count(popcount). We present a charge sharing XNOR and popcount operation in 10transistor SRAM cells. We have employed multiple circuit techniques includingdual-read-worldines (Dual-RWL) along with a dual-stage ADC that overcomes theinaccuracies of a low precision ADC, to achieve a fairly accurate popcount. Inaddition, a key highlight of the present work is the fact that we proposesectioning of the SRAM array by adding switches onto the read-bitlines, therebyachieving improved parallelism. This is beneficial for deep networks, where thekernel size grows and requires to be stored in multiple sub-banks. As such, oneneeds to evaluate the partial popcount from multiple sub-banks and sum them upfor achieving the final popcount. For n-sections per sub-array, we can performn convolutions within one particular sub-bank, thereby improving overall systemthroughput as well as the energy efficiency. Our results at the array levelshow that the energy consumption and delay per-operation was 1.914pJ and 45ns,respectively. Moreover, an energy improvement of 2.5x, and a performanceimprovement of 4x was achieved by using the proposed sectioned-SRAM, comparedto a non-sectioned SRAM design.

Xcel-RAM: Accelerating Binary Neural Networks in High-Throughput SRAM Compute Arrays