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High parallel framework has been proved to be very suitable for graphprocessing. There are various work to optimize the implementation in FPGAs, apipeline parallel device. The key to make use of the parallel performance ofFPGAs is to process graph data in pipeline model and take advantage of on-chipmemory to realize necessary locality process. This paper proposes a modularizegraph processing framework, which focus on the whole executing procedure withthe extremely different degree of parallelism. The framework has threecontributions. First, the combination of vertex-centric and edge-centricprocessing framework can been adjusting in the executing procedure toaccommodate top-down algorithm and bottom-up algorithm. Second, owing to thepipeline parallel and finite on-chip memory accelerator, the novel edge-block,a block consist of edges vertex, achieve optimizing the way to utilize theon-chip memory to group the edges and stream the edges in a block to realizethe stream pattern to pipeline parallel processing. Third, depending to theanalysis of the block structure of nature graph and the executingcharacteristics during graph processing, we design a novel conversiondispatcher to change processing module, to match the corresponding exchangepoint.

An Efficient Dispatcher for Large Scale GraphProcessing on OpenCL-based FPGAs