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To cope with the enhanced luminosity at the Large Hadron Collider (LHC) in2021, the ATLAS collaboration is planning a major detector upgrade. As a partof this, the Level 1 trigger based on calorimeter data will be upgraded toexploit the fine granularity readout using a new system of Feature EXtractors(FEX), which each reconstruct different physics objects for the triggerselection. The jet FEX (jFEX) system is conceived to provide jet identification(including large area jets) and measurements of global variables within alatency budget of less then 400ns. It consists of 6 modules. A single jFEXmodule is an ATCA board with 4 large FPGAs of the Xilinx Ultrascale+ family,that can digest a total input data rate of ~3.6 Tb/s using up to 120 MultiGigabit Transceiver (MGT), 24 electrical optical devices, board control andpower on the mezzanines to allow flexibility in upgrading controls functionsand components without affecting the main board. The 24-layers stack-up wascarefully designed to preserve the signal integrity in a very densely populatedhigh speed signal board selecting MEGTRON6 as the most suitable PCB material.This contribution reports on the design challenges and the test results of thejFEX prototypes. In particular the fully assembled final prototype has beentested up to 12.8 Gb/s in house and in integrated tests at CERN. The full jFEXsystem will be produced by the end of 2018 to allow for installation andcommissioning to be completed before LHC restarts in March 2021.

A new high speed, Ultrascale+ based board for the ATLAS jet calorimeter trigger system