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The Level-1 Muon Barrel Trigger of the ATLAS Experiment at LHC makes use ofResistive Plate Chamber (RPC) detectors. The on-detector trigger electronicsmodules are able to identify muons with predefined transverse momentum values(pT) by executing a coincidence logic on signals coming from the variousdetector layers. Then, on-detector trigger boards transfer trigger data to theoff-detector electronics. A complex trigger system processes the incoming databy combining trigger information from the Barrel and the End-cap regions, andby providing the combined muon candidate to the Central Trigger Processor(CTP). For almost a decade, the Level-1 Trigger system has been operating verywell, despite the challenging requirements on trigger efficiency andperformance, and the continuously increasing LHC luminosity. In order to copewith these constraints, various upgrades for the full trigger system werealready deployed, and others have been designed to be installed in the nextyears. Most of the upgrades to the trigger system rely on state-of-the-arttechnologies, thus allowing to increase the processing power and data transferbandwidth, and to design more complex trigger menus. As a consequence, moretrigger candidates might be selected by the system, thus supporting new physicsstudies or topological selections. In this work, we discuss the design of thefirst prototype of the new Barrel Interface Board, designed around a XilinxFPGA, which will be used to transfer RPC trigger data to the CTP system. Themain requirement for the board is to support the optical transmission of thetrigger data with fixed latency and to allow the implementation of new triggeralgorithms. We describe the hardware implementation and the results of thefirst functional and integration tests.

The Phase-1 Upgrade for the Level-1 Muon Barrel Trigger of the ATLAS Experiment at LHC