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The detector readout architecture introduced in this paper is intended forsmall to medium size physics experiments that have moderate bandwidth needs,and applications that require an ultimately low background radioactivity forthe parts close to the detector. The first idea to simplify the readout systemand minimize material budget is to use a common fanout structure to transportfrom the off-detector back-end electronics all the traffic required for thesynchronization, configuration and readout of the front-end electronics. Thesecond idea is to use between each front-end card and the back-end electronicsa point-to-point link that runs at the relatively low speed that suffices forthe target application. This broadens the possible choices for the physicalmedia of the communication links, e.g. glass fiber, plastic optical fiber, orcopper. This paper presents a communication protocol adequate for the proposedasymmetric network and shows the design of a back-end unit capable ofcontrolling 32 front-end units at up to 12.8 Gbps of aggregate bandwidth usingan inexpensive commercial FPGA module where the large number of regular I/Opins interface to the front-end links, while the few available multi-gigabitper second capable transceivers are affected to the communication with theupper stage of the DAQ system.

Back-end Electronics for Low Background and Medium Scale Physics Experiments Based on an Asymmetric Network