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Modern processors utilize an increasingly large register set to facilitateefficient floating point and SIMD computation. This large register set is aburden for operating systems, as its content needs to be saved and restoredwhen the operating system context switches between tasks. As an optimization,the operating system can defer the context switch of the FPU and SIMD registerset until the first instruction is executed that needs access to theseregisters. Meanwhile, the old content is left in place with the hope that thecurrent task might not use these registers at all. This optimization iscommonly called lazy FPU context switching. To make it possible, a processoroffers the ability to toggle the availability of instructions utilizingfloating point and SIMD registers. If the instructions are turned off, anyattempt of executing them will generate a fault.  In this paper, we present an attack that exploits lazy FPU context switchingand allows an adversary to recover the FPU and SIMD register set of arbitraryprocesses or VMs. The attack works on processors that transiently execute FPUor SIMD instructions that follow an instruction generating the fault indicatingthe first use of FPU or SIMD instructions. On operating systems using lazy FPUcontext switching, the FPU and SIMD register content of other processes orvirtual machines can then be reconstructed via cache side effects.  With SIMD registers not only being used for cryptographic computation, butalso increasingly for simple operations, such as copying memory, we argue thatlazy FPU context switching is a dangerous optimization that needs to be turnedoff in all operating systems, if there is a chance that they run on affectedprocessors.

LazyFP: Leaking FPU Register State using Microarchitectural Side-Channels