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The Address in Real Time Data Driver Card (ADDC) is designed to transmit thetrigger data in the Micromegas detector of the ATLAS New Small Wheel (NSW)upgrade. The ART signals are generated by the front end ASIC, named VMM chip,to indicate the address of the first above-threshold event. A custom ASIC (ARTASIC) is designed to receive the ART signals from the VMM chip and do thehit-selection processing. Processed data from ART ASIC will be transmitted outof the NSW detector through GBTx serializer, VTTx optical transmitter moduleand fiber optical links. The ART signal is critical for the ATLAS experimenttrigger selection thus the functionality and stability of the ADDC is veryimportant. To ensure extensive testing of the ADDC, an FMC based testingplatform and special firmware/software are developed. This test platform workswith the commercial Xilinx VC707 FPGA develop kit, even without the otherelectronics of the NSW it can test all the functionality of the ADDC and alsolong term stability. This paper will introduce the design, testing procedureand results from the ADDC and the FMC testing platform.

The Design and Testing of the Address in Real Time Data Driver Card for the Micromegas Detector of the ATLAS New Small Wheel Upgrade