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The Pad Front End Board (pFEB) and the Strip Front End Board (sFEB) aredeveloped for the ATLAS Phase-I sTGC Trigger Upgrade. The pFEB is used to togather and analyze pads trigger, and the sFEB is developed to accept the padtrigger to define the regions-of-interest for strips readout. The performanceof p/sFEBs must be confirmed before they are mounted on the sTGC detector. Wewill present the scanning test system prototype which is designed according tothe test requirements of the p/sFEB. In this test system prototype, asimulation signal board is developed to generate different types of signal tothe p/sFEB. PC software and FPGA XADC cooperate to achieve the scan test ofanalog parameter.

Scanning Test System Prototype of p/sFEB for the ATLAS Phase-I sTGC Trigger Upgrade