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Pattern matching design verification has gained noticeable attention insemiconductor technologies as it can precisely identify more localizedproblematic areas (weakpoints) in the layout. To address these weakpoints,engineers adopt 'Rip-up and Reroute' methodology to reroute the nets and avoidthese weakpoints. However, the technique is unable to address weakpoints due tothe cell placement. The only present approach is to manually shift or flip thestandard cells to eradicate the weakpoint. To overcome the challenge in goingfrom a manual and laborious process to a fully automated fixing, we haveproposed an in-design auto-fixing feature, tested with the commercial designtool, Synopsys IC Compiler. Our experimental result has demonstrated close toone hundred percent lithography weakpoints fixing on all of our 14nm designs.

Advanced In-Design Auto-Fixing Flow for Cell Abutment Pattern Matching Weakpoints