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This paper summarizes our work on experimentally characterizing, mitigating,and recovering read disturb errors in multi-level cell (MLC) NAND flash memory,which was published in DSN 2015, and examines the work's significance andfuture potential. NAND flash memory reliability continues to degrade as thememory is scaled down and more bits are programmed per cell. A key contributorto this reduced reliability is read disturb, where a read to one row of cellsimpacts the threshold voltages of unread flash cells in different rows of thesame block.  For the first time in open literature, this work experimentally characterizesread disturb errors on state-of-the-art 2Y-nm (i.e., 20-24 nm) MLC NAND flashmemory chips. Our findings (1) correlate the magnitude of threshold voltageshifts with read operation counts, (2) demonstrate how program/erase cyclecount and retention age affect the read-disturb-induced error rate, and (3)identify that lowering pass-through voltage levels reduces the impact of readdisturb and extend flash lifetime. Particularly, we find that the probabilityof read disturb errors increases with both higher wear-out and higherpass-through voltage levels.  We leverage these findings to develop two new techniques. The first techniquemitigates read disturb errors by dynamically tuning the pass-through voltage ona per-block basis. Using real workload traces, our evaluations show that thistechnique increases flash memory endurance by an average of 21%. The secondtechnique recovers from previously-uncorrectable flash errors by identifyingand probabilistically correcting cells susceptible to read disturb errors. Ourevaluations show that this recovery technique reduces the raw bit error rate by36%.

Read Disturb Errors in MLC NAND Flash Memory