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This paper summarizes the SoftMC DRAM characterization infrastructure, whichwas published in HPCA 2017, and examines the work's significance and futurepotential.  SoftMC (Soft Memory Controller) is the first publicly-available DRAM testinginfrastructure that can flexibly and efficiently test DRAM chips in a manneraccessible to both software and hardware developers. SoftMC is an FPGA-basedtesting platform that can control and test memory modules designed for thecommonly-used DDR (Double Data Rate) interface. SoftMC has two key properties:(i) it provides flexibility to thoroughly control memory behavior or toimplement a wide range of mechanisms using DDR commands; and (ii) it is easy touse as it provides a simple and intuitive high-level programming interface forusers, completely hiding the low-level details of the FPGA.  We demonstrate the capability, flexibility, and programming ease of SoftMCwith two example use cases. First, we implement a test that characterizes theretention time of DRAM cells. Second, we show that the expected latencyreduction of two recently-proposed mechanisms, which rely on accessingrecently-refreshed or recently-accessed DRAM cells faster than other DRAMcells, is not observable in existing DRAM chips.  Various versions of the SoftMC platform have enabled many of our other DRAMcharacterization studies. We discuss several other use cases of SoftMC,including the ability to characterize emerging non-volatile memory modules thatobey the DDR standard. We hope that our open-source release of SoftMC fills agap in the space of publicly-available experimental memory testinginfrastructures and inspires new studies, ideas, and methodologies in memorysystem design.

SoftMC: Practical DRAM Characterization Using an FPGA-Based Infrastructure