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This paper summarizes the idea of Low-Cost Interlinked Subarrays (LISA),which was published in HPCA 2016, and examines the work's significance andfuture potential. Contemporary systems perform bulk data movement movementinefficiently, by transferring data from DRAM to the processor, and then backto DRAM, across a narrow off-chip channel. The use of this narrow channelresults in high latency and energy consumption. Prior work proposes to avoidthese high costs by exploiting the existing wide internal DRAM bandwidth forbulk data movement, but the limited connectivity of wires within DRAM allowsfast data movement within only a single DRAM subarray. Each subarray is only afew megabytes in size, greatly restricting the range over which fast bulk datamovement can happen within DRAM.  Our HPCA 2016 paper proposes a new DRAM substrate, Low-Cost Inter-LinkedSubarrays (LISA), whose goal is to enable fast and efficient data movementacross a large range of memory at low cost. LISA adds low-cost connectionsbetween adjacent subarrays. By using these connections to interconnect theexisting internal wires (bitlines) of adjacent subarrays, LISA enableswide-bandwidth data transfer across multiple subarrays with little (only 0.8%)DRAM area overhead. As a DRAM substrate, LISA is versatile, enabling a varietyof new applications. We describe and evaluate three such applications indetail: (1) fast inter-subarray bulk data copy, (2) in-DRAM caching using aDRAM architecture whose rows have heterogeneous access latencies, and (3)accelerated bitline precharging by linking multiple precharge units together.Our extensive evaluations show that each of LISA's three applicationssignificantly improves performance and memory energy efficiency on a variety ofworkloads and system configurations.

LISA: Increasing Internal Connectivity in DRAM for Fast Data Movement and Low Latency