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This paper summarizes our work on experimental characterization and analysisof reduced-voltage operation in modern DRAM chips, which was published inSIGMETRICS 2017, and examines the work's significance and future potential.  We take a comprehensive approach to understanding and exploiting the latencyand reliability characteristics of modern DRAM when the DRAM supply voltage islowered below the nominal voltage level specified by DRAM standards. We performan experimental study of 124 real DDR3L (low-voltage) DRAM chips manufacturedrecently by three major DRAM vendors. We find that reducing the supply voltagebelow a certain point introduces bit errors in the data, and we comprehensivelycharacterize the behavior of these errors. We discover that these errors can beavoided by increasing the latency of three major DRAM operations (activation,restoration, and precharge). We perform detailed DRAM circuit simulations tovalidate and explain our experimental findings. We also characterize thevarious relationships between reduced supply voltage and error locations,stored data patterns, DRAM temperature, and data retention.  Based on our observations, we propose a new DRAM energy reduction mechanism,called Voltron. The key idea of Voltron is to use a performance model todetermine by how much we can reduce the supply voltage without introducingerrors and without exceeding a user-specified threshold for performance loss.Our evaluations show that Voltron reduces the average DRAM and system energyconsumption by 10.5% and 7.3%, respectively, while limiting the average systemperformance loss to only 1.8%, for a variety of memory-intensive quad-coreworkloads. We also show that Voltron significantly outperforms prior dynamicvoltage and frequency scaling mechanisms for DRAM.

Voltron: Understanding and Exploiting the Voltage-Latency-Reliability Trade-Offs in Modern DRAM Chips to Improve Energy Efficiency