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Both industry and academia have extensively investigated hardwareaccelerations. In this work, to address the increasing demands in computationalcapability and memory requirement, we propose structured weight matrices(SWM)-based compression techniques for both \emph{field programmable gatearray} (FPGA) and \emph{application-specific integrated circuit} (ASIC)implementations. In algorithm part, SWM-based framework adopts block-circulantmatrices to achieve a fine-grained tradeoff between accuracy and compressionratio. The SWM-based technique can reduce computational complexity fromO($n^2$) to O($n\log n$) and storage complexity from O($n^2$) to O($n$) foreach layer and both training and inference phases. For FPGA implementations ondeep convolutional neural networks (DCNNs), we achieve at least 152X and 72Ximprovement in performance and energy efficiency, respectively using theSWM-based framework, compared with the baseline of IBM TrueNorth processorunder same accuracy constraints using the data set of MNIST, SVHN, andCIFAR-10. For FPGA implementations on long short term memory (LSTM) networks,the proposed SWM-based LSTM can achieve up to 21X enhancement in performanceand 33.5X gains in energy efficiency compared with the baseline accelerator.For ASIC implementations, the SWM-based ASIC design exhibits impressiveadvantages in terms of power, throughput, and energy efficiency. Experimentalresults indicate that this method is greatly suitable for applying DNNs ontoboth FPGAs and mobile/IoT devices.

Structured Weight Matrices-Based Hardware Accelerators in Deep Neural Networks: FPGAs and ASICs