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Non-volatile memory (NVM) is a class of promising scalable memorytechnologies that can potentially offer higher capacity than DRAM at the samecost point. Unfortunately, the access latency and energy of NVM is often higherthan those of DRAM, while the endurance of NVM is lower. Many DRAM-NVM hybridmemory systems use DRAM as a cache to NVM, to achieve the low access latency,low energy, and high endurance of DRAM, while taking advantage of the largecapacity of NVM. A key question for a hybrid memory system is what data tocache in DRAM to best exploit the advantages of each technology while avoidingthe disadvantages of each technology as much as possible.  We propose a new memory controller design that improves hybrid memoryperformance and energy efficiency. We observe that both DRAM and NVM banksemploy row buffers that act as a cache for the most recently accessed memoryrow. Accesses that are row buffer hits incur similar latencies (and energyconsumption) in both DRAM and NVM, whereas accesses that are row buffer missesincur longer latencies (and higher energy consumption) in NVM than in DRAM. Toexploit this, we devise a policy that caches heavily-reused data thatfrequently misses in the NVM row buffers into DRAM. Our policy tracks the rowbuffer miss counts of recently-used rows in NVM, and caches in DRAM the rowsthat are predicted to incur frequent row buffer misses. Our proposed policyalso takes into account the high write latencies of NVM, in addition to rowbuffer locality and more likely places the write-intensive pages in DRAMinstead of NVM.

A Memory Controller with Row Buffer Locality Awareness for Hybrid Memory Systems