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Boltzmann tyranny poses a fundamental limit to lowering the energydissipation of conventional MOS devices, a minimum increase of the gatevoltage, i.e. 60 mV, is required for a 10-fold increase in drain-to-sourcecurrent at 300 K. Negative Capacitance (NC) in ferroelectric materials isproposed in order to address this physical limitation of CMOS technology. Apolarization destabilization in ferroelectrics causes an effective negativepermittivity, resulting in a differential voltage amplification and a reducedsubthreshold swing when integrated into the gate stack of a transistor. Recentdemonstrations of negative capacitance concerned mainly n-type MOSFETs andtheir subthreshold slope. An effective technology booster should be capable ofimproving the performance of both n- and p-type transistors. In this work, wereport a significant enhancement in both digital (subthreshold swing,on-current over off-current ratio, and overdrive) and analog (transconductanceand current efficiency factor) FoM of commercial 28nm CMOS process byexploiting a PZT capacitor as the negative capacitance booster. Accordingly, asub-thermal swing down to 10 mV/decade together with an enhanced currentefficiency factor up to 10$^5$ V$^{-1}$ is obtained in both n- and p-typeMOSFETs at room temperature. The overdrive voltage is enhanced up to 0.45 V,leading to a supply voltage reduction of 50\%.

Negative Capacitance as Digital and Analog Performance Booster for Complementary MOS Transistors