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Deep learning algorithms have shown tremendous success in many recognitiontasks; however, these algorithms typically include a deep neural network (DNN)structure and a large number of parameters, which makes it challenging toimplement them on power/area-constrained embedded platforms. To reduce thenetwork size, several studies investigated compression by introducingelement-wise or row-/column-/block-wise sparsity via pruning andregularization. In addition, many recent works have focused on reducingprecision of activations and weights with some reducing down to a single bit.However, combining various sparsity structures with binarized orvery-low-precision (2-3 bit) neural networks have not been comprehensivelyexplored. In this work, we present design techniques for minimum-area/-energyDNN hardware with minimal degradation in accuracy. During training, bothbinarization/low-precision and structured sparsity are applied as constraintsto find the smallest memory footprint for a given deep learning algorithm. TheDNN model for CIFAR-10 dataset with weight memory reduction of 50X exhibitsaccuracy comparable to that of the floating-point counterpart. Area,performance and energy results of DNN hardware in 40nm CMOS are reported forthe MNIST dataset. The optimized DNN that combines 8X structured compressionand 3-bit weight precision showed 98.4% accuracy at 20nJ per classification.

Minimizing Area and Energy of Deep Learning Hardware Design Using Collective Low Precision and Structured Compression