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Despite the impressive search rate of one key per clock cycle, the updatestage of a random-access-memory-based content-addressable-memory (RAM-basedCAM) always suffers high latency. Two primary causes of such latency include:(1) the compulsory erasing stage along with the writing stage and (2) the majordifference in data width between the RAM-based CAM (e.g., 8-bit width) and themodern systems (e.g., 256-bit width). This brief, therefore, aims for anefficient input/output (I/O) architecture of RAM-based binary CAM (RCAM) forlow-latency update. To achieve this goal, three techniques, namely centralizederase RAM, bit-sliced, and hierarchical-partitioning, are proposed to eliminatethe latency of erasing stage, as well as to allow RCAM to exploit the bandwidthof modern systems effectively. Several RCAMs, whose data width ranges from 8bits to 64 bits, were integrated into a 256-bit system for the evaluation. Theexperimental results in an Intel Arria V 5ASTFD5 FPGA prove that at 100 MHz,the proposed designs achieve at least 9.6 times higher I/O efficiency ascompared to the traditional RCAM.

An Efficient I/O Architecture for RAM-based Content-Addressable Memory on FPGA