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Design of next generation computer systems should be supported by simulationinfrastructure that must achieve a few contradictory goals such as fastexecution time, high accuracy, and enough flexibility to allow comparisonbetween large numbers of possible design points. Most existing architecturelevel simulators are designed to be flexible and to execute the code inparallel for greater efficiency, but at the cost of scarified accuracy. Thispaper presents the ScaleSimulator simulation environment, which is based on anew design methodology whose goal is to achieve near cycle accuracy while stillbeing flexible enough to simulate many different future system architecturesand efficient enough to run meaningful workloads. We achieve these goals bymaking the parallelism a first-class citizen in our methodology. Thus, thispaper focuses mainly on the ScaleSimulator design points that enable betterparallel execution while maintaining the scalability and cycle accuracy of asimulated architecture. The paper indicates that the new proposedScaleSimulator tool can (1) efficiently parallelize the execution of acycle-accurate architecture simulator, (2) efficiently simulate complexarchitectures (e.g., out-of-order CPU pipeline, cache coherency protocol, andnetwork) and massive parallel systems, and (3) use meaningful workloads, suchas full simulation of OLTP benchmarks, to examine future architectural choices.

ScaleSimulator: A Fast and Cycle-Accurate Parallel Simulator for Architectural Exploration