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It is a challenging task to deploy computationally and memory intensiveState-of-the-art deep neural networks (DNNs) on embedded systems with limitedhardware resources and power budgets. Recently developed techniques like DeepCompression make it possible to fit large DNNs, such as AlexNet and VGGNet,fully in on-chip SRAM. But sparse networks compressed using existing encodingformats, like CSR or CSC, complex the computation at runtime due to theirirregular memory access characteristics. In [1], we introduce a computationdataflow, stacked filters stationary dataflow (SFS), and a corresponding dataencoding format, relative indexed compressed sparse filter format (CSF), tomake the best of data sparsity, and simplify data handling at execution time.In this paper we present FPGA implementations of these methods. We implementseveral compact streaming fully connected (FC) and Convolutional (CONV) neuralnetwork processors to show their efficiency. Comparing with thestate-of-the-art results [2,3,4], our methods achieve at least 2x improvementfor computation efficiency per PE on most layers. Especially, our methodsachieve 8x improvement on AlexNet layer CONV4 with 384 filters, and 11ximprovement on VGG16 layer CONV5-3 with 512 filters.

FPGA Implementations of 3D-SIMD Processor Architecture for Deep Neural  Networks Using Relative Indexed Compressed Sparse Filter Encoding Format and  Stacked Filters Stationary Flow