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The functions of the Low-Level Radio Frequency (LLRF) system at EuropeanSpallation Source (ESS) are implemented on different Field-Programmable GateArray (FPGA) boards in a Micro Telecommunications Computing Architecture (MTCA)crate. Besides the algorithm, code that provides access to the peripheralsconnected to the FPGA is necessary. In order to provide a common platform forthe FPGA developments at ESS - the ESS FPGA Framework has been designed. Theframework facilitates the integration of different algorithms on different FPGAboards. Three functions are provided by the framework: (1) Communicationinterfaces to peripherals, e.g. Analog-to-Digital Converters (ADCs) andon-board memory, (2) Upstream communication with the control system overPeripheral Component Interconnect Express (PCIe), and (3) Configuration of theon-board peripherals. To keep the framework easily extensible by IntellectualProperty (IP) blocks and to enable seamless integration with the Xilinx designtools, the Advanced eXtensible Interface version 4 (AXI4) bus is the chosencommunication interconnect. Furthermore, scripts automatize the building of theFPGA configuration, software components and the documentation. The LLRF controlalgorithms have been successfully integrated into the framework.

The ESS FPGA Framework and its Application on the ESS LLRF System