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Applications of Trigger Units (TU) can be found in almost all accelerators atCERN. The requirements in terms of operating frequencies, configuration ormodes of operation change from one application to another, how-ever, in termsof design requirements for the Trigger Unit, the operating frequency isprobably the most demanding one. In this work, we present an implementation ofa Trigger Unit almost fully embedded in the FPGA logic operating at a maximumfrequency of 1 GHz using the internal serializer/deserializer circuitry tosimplify the timing constraints of the design. This implementation allows easyreconfiguration of the module and the development of new modes of operation,which are described in this paper.

A 1 GHz RF Trigger Unit implemented in FPGA logic