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The High-Luminosity LHC will provide the unique opportunity to explore thenature of physics beyond the Standard Model of strong and electroweakinteractions. Highly selective first level triggers are essential for thephysics programme of the ATLAS experiment at the HL-LHC where the instantaneousluminosity will exceed the LHC Run 1 instantaneous luminosity by almost anorder of magnitude. The ATLAS first level muon trigger rate is dominated by lowmomentum muons, selected due to the moderate momentum resolution of theresistive plate and thin gap trigger chambers. This limitation can be overcomeby including the data of the precision muon drift tube (MDT) chambers in thefirst level trigger decision. This requires the fast continuous transfer of theMDT hits to the off-detector trigger logic and a fast track reconstructionalgorithm performed in the trigger logic.  In order to demonstrate the feasibility of reconstructing tracks in MDTchambers within the short available first-level trigger latency of about3~$\mu$s we implemented a seeded Hough transform on the ARM Cortex A9microprocessor of a Xilinx Zynq FPGA and studied its performance with test-beamdata recorded in CERN's Gamma Irradiation Facility. We could show that by usingthe ARM processor's Neon Single Instruction Multiple Data Engine to carry out 4floating point operations in parallel the challenging latency requirement canbe matched.

Hardware Implementation of a Fast Algorithm for the Reconstruction of  Muon Tracks in ATLAS Muon Drift-Tube Chambers for the First-Level Muon  Trigger at the HL-LHC