English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

Hardware accelerations of deep learning systems have been extensivelyinvestigated in industry and academia. The aim of this paper is to achieveultra-high energy efficiency and performance for hardware implementations ofdeep neural networks (DNNs). An algorithm-hardware co-optimization framework isdeveloped, which is applicable to different DNN types, sizes, and applicationscenarios. The algorithm part adopts the general block-circulant matrices toachieve a fine-grained tradeoff between accuracy and compression ratio. Itapplies to both fully-connected and convolutional layers and contains amathematically rigorous proof of the effectiveness of the method. The proposedalgorithm reduces computational complexity per layer from O($n^2$) to O($n\logn$) and storage complexity from O($n^2$) to O($n$), both for training andinference. The hardware part consists of highly efficient Field ProgrammableGate Array (FPGA)-based implementations using effective reconfiguration, batchprocessing, deep pipelining, resource re-using, and hierarchical control.Experimental results demonstrate that the proposed framework achieves at least152X speedup and 71X energy efficiency gain compared with IBM TrueNorthprocessor under the same test accuracy. It achieves at least 31X energyefficiency gain compared with the reference FPGA-based work.

Towards Ultra-High Performance and Energy Efficiency of Deep Learning Systems: An Algorithm-Hardware Co-Optimization Framework