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With the ever-growing storage density, high-speed, and low-cost data access,flash memory has inevitably become popular. Multi-level cell (MLC) NAND flashmemory, which can well balance the data density and memory stability, hasoccupied the largest market share of flash memory. With the aggressive memoryscaling, however, the reliability decays sharply owing to multipleinterferences. Therefore, the control system should be embedded with a suitableerror correction code (ECC) to guarantee the data integrity and accuracy. Weproposed the pre-check scheme which is a multi-strategy polar code scheme tostrike a balance between reasonable frame error rate (FER) and decodinglatency. Three decoders namely binary-input, quantized-soft, and pure-softdecoders are embedded in this scheme. Since the calculation of softlog-likelihood ratio (LLR) inputs needs multiple sensing operations andoptional quantization boundaries, a 2-bit quantized hard-decision decoder isproposed to outperform the hard-decoded LDPC bit-flipping decoder with fewersensing operations. We notice that polar codes have much lower computationalcomplexity compared to LDPC codes. The stepwise maximum mutual information(SMMI) scheme is also proposed to obtain overlapped boundaries withoutexhausting search. The mapping scheme using Gray code is employed and proved toachieve better raw error performance compared to other alternatives. Hardwarearchitectures are also given in this paper.

Polar-Coded Forward Error Correction for MLC NAND Flash Memory Polar FEC for NAND Flash Memory