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In this paper, we develop a analytical model and algorithm for calculatinguneven current distribution in via array structures. We propose a stress timetranslation formula and cumulative failure distribution equation to model thememory effect of electro migration stress or damage on a via array structure.We develop a method to project via array electromigration (EM) lifetime basedon an arbitrary via failure sequence, and demonstrate that the proposed viaarray EM lifetime distribution trend correlates well with experimental results.

Modeling and Simulation of Electromigration Behavior for Via Array Structure