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Approximate computing is emerging as an alternative to accurate computing dueto its potential for realizing digital circuits and systems with low powerdissipation, less critical path delay, and less area occupancy for anacceptable trade-off in the accuracy of results. In the domain of computerarithmetic, several approximate adders and multipliers have been designed andtheir potential have been showcased versus accurate adders and multipliers forpractical digital signal processing applications. Nevertheless, in the existingliterature, almost all the approximate adders and multipliers reportedcorrespond to the synchronous design method. In this work, we consider robustasynchronous i.e. quasi-delay-insensitive realizations of approximate adders byemploying delay-insensitive codes for data representation and processing, andthe 4-phase handshake protocols for data communication. The 4-phase handshakeprotocols used are the return-to-zero and the return-to-one protocols.Specifically, we consider the implementations of 32-bit approximate addersbased on the return-to-zero and return-to-one handshake protocols by adoptingthe delay-insensitive dual-rail code for data encoding. We consider a range ofapproximations varying from 4-bits to 20-bits for the least significantpositions of the accurate 32-bit asynchronous adder. The asynchronous adderscorrespond to early output (i.e. early reset) type, which are based on thewell-known ripple carry adder architecture. The experimental results show thatapproximate asynchronous adders achieve reductions in the design metrics suchas latency, cycle time, average power dissipation, and silicon area compared tothe accurate asynchronous adders. Further, the reductions in the design metricsare greater for the return-to-one protocol compared to the return-to-zeroprotocol. The design metrics were estimated using a 32/28nm CMOS technology.

Approximate Early Output Asynchronous Adders Based on Dual-Rail Data Encoding and 4-Phase Return-to-Zero and Return-to-One Handshaking