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With ever-increasing application of machine learning models in variousdomains such as image classification, speech recognition and synthesis, andhealth care, designing efficient hardware for these models has gained a lot ofpopularity. While the majority of researches in this area focus on efficientdeployment of machine learning models (a.k.a inference), this work concentrateson challenges of training these models in hardware. In particular, this paperpresents a high-performance, scalable, reconfigurable solution for bothtraining and deployment of different dimensionality reduction models inhardware by introducing a hardware-friendly algorithm. Compared tostate-of-the-art implementations, our proposed algorithm and its hardwarerealization decrease resource consumption by 50\% without any degradation inaccuracy.

A Hardware-Friendly Algorithm for Scalable Training and Deployment of Dimensionality Reduction Models on FPGA