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In modern digital circuit back-end design, designers heavily rely onelectronic-design-automoation (EDA) tool to close timing. However, theheuristic algorithms used in the place and route tool usually does not resultin optimal solution. Thus, significant design effort is used to tune parametersor provide user constraints or guidelines to improve the tool performance. Inthis paper, we targeted at those optimization space left behind by the EDAtools and propose a machine learning framework that helps to define what arethe guidelines and constraints for registers placement, which can yield betterperformance and quality for back-end design. In other words, the framework istrying to learn what are the flaws of the existing EDA tools and tries tooptimize it by providing additional information. We discuss what is the properinput feature vector to be extracted, and what is metric to be used forreference output. We also develop a scheme to generate perturbed trainingsamples using existing design based on Gaussian randomization. By applying ourmethodology, we are able to improve the design runtime by up to 36% and timingquality by up to 23%.

A Machine Learning Framework for Register Placement Optimization in Digital Circuit Design