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This paper presents a general framework for auto-generation of pipelinedpolar encoder architectures. The proposed framework could be well representedby a general formula. Given arbitrary code length $N$ and the level ofparallelism $M$, the formula could specify the corresponding hardwarearchitecture. We have written a compiler which could read the formula and thenautomatically generate its register-transfer level (RTL) description suitablefor FPGA or ASIC implementation. With this hardware generation system, onecould explore the design space and make a trade-off between cost andperformance. Our experimental results have demonstrated the efficiency of thisauto-generator for polar encoder architectures.

Auto-Generation of Pipelined Hardware Designs for Polar Encoder