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Unpredictable Kirkendall void formation at the interface of circuitinterconnections underlies degradation in electronics, yet there is a lack ofeffective approaches to curb the amount of these voids. Here we developed astrain-anneal method to tailor grain size distributions in the copper substrateof interconnections, and demonstrate quantitatively that not only the removalof the impurities but also an increase in the grain size of the substratesleads to an appreciable decline in the void density. The interconnections onthe substrate recrystallized at a high annealing temperature show the massiveporosity and the increased sensitivity of the voiding to the grain size. Ourfindings have broad implications for manipulation of void propensity in manyother hetero-interfaces and are essential for high-performance circuit bondingin high temperature/high power electronic devices based on wide band gapsemiconductors.

Suppressing Kirkendall Void Density in Circuit Interconnections by Strain Annealing