English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Global: Zendy Plus annual

Presents the access of premium content as premium feature

Premium Content

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the summarisation as premium feature

Summarisation

Insights

Presents the pdf analysis as premium feature

PDF Analysis

Presents the zaia usage as premium feature

ZAIA

Global: Zendy Plus monthly

Global: Zendy Tools annual

Global: Zendy Tools monthly

Global: Zendy Free Plan

Heterogeneous embedded systems on chip (HESoCs) co-integrate a standard hostprocessor with programmable manycore accelerators (PMCAs) to combinegeneral-purpose computing with domain-specific, efficient processingcapabilities. While leading companies successfully advance their HESoCproducts, research lags behind due to the challenges of building a prototypingplatform that unites an industry-standard host processor with an open researchPMCA architecture. In this work we introduce HERO, an FPGA-based researchplatform that combines a PMCA composed of clusters of RISC-V cores, implementedas soft cores on an FPGA fabric, with a hard ARM Cortex-A multicore hostprocessor. The PMCA architecture mapped on the FPGA is silicon-proven,scalable, configurable, and fully modifiable. HERO includes a complete softwarestack that consists of a heterogeneous cross-compilation toolchain with supportfor OpenMP accelerator programming, a Linux driver, and runtime libraries forboth host and PMCA. HERO is designed to facilitate rapid exploration on allsoftware and hardware layers: run-time behavior can be accurately analyzed bytracing events, and modifications can be validated through fully automated hardware and software builds and executed tests. We demonstrate the usefulness ofHERO by means of case studies from our research.

HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA