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This paper outlines an FPGA VLSI design methodology that was used to realizea fully functioning FPGA chip in 130nm CMOS with improved routability andmemory robustness. The architectural design space exploration and synthesiscapability were enabled by the Verilog-to-Routing CAD tool. The capabilities ofthis tool were extended to enable bitstream generation and deployment. Tovalidate the architecture and bitstream implementation, a Chisel (ConstructingHardware in the Embedded Scala Language) model of the FPGA was created torapidly verify the microarchitectural details of the device prior to schematicdesign. A custom carrier board and configuration tool were used to verifycorrect operational characteristics of the FPGA over various resourceutilizations and clock frequencies.

FPGA with Improved Routability and Robustness in 130nm CMOS with Open-Source CAD Targetability